/*****************************************************************/ 00500000 /* */ 01000000 /* @Y30LB52*/ 01500000 /* THE FOLLOWING VARIABLES AND STRUCTURES MAP THE VARIABLE */ 02000000 /* CONFIGURATION DATA PRODUCED BY THE 'ISDACNFG' ROUTINE. THE */ 02500000 /* TABLES ARE ANCHORED BY POINTERS IN THE FIXED CONFIGURATION */ 03000000 /* STRUCTURE. @Y30LB52*/ 03500000 /* @Y30LB52*/ 04000000 /* */ 04500000 /*****************************************************************/ 05000000 05500000 DCL 06000000 06500000 /***************************************************************/ 07000000 /* */ 07500000 /* @Y30LB52*/ 08000000 /* THE FOLLOWING IS A BASED VARIABLE MAPPING THE 16 POSSIBLE */ 08500000 /* CPU SERIAL ID'S ATTACHED TO THE SUBSYSTEM IN THE @Y30LB52*/ 09000000 /* CONFIGURATION DESCRIBED. EACH SERIAL IS 5 BYTES. @Y30LB52*/ 09500000 /* @Y30LB52*/ 10000000 /* */ 10500000 /***************************************************************/ 11000000 11500000 CPUSERS CHAR(80) BASED(CPUSERAD),/* CPU SERIALS @Y30LB52*/ 12000000 12500000 /***************************************************************/ 13000000 /* */ 13500000 /* @Y30LB52*/ 14000000 /* THIS STRUCTURE MAPS THE LOGICAL CONFIGURATION OF THE SS/1 */ 14500000 /* DRC'S AND DRD'S ONTO THE PHYSICAL CONFIGURATION THIS@Y30LB52*/ 15000000 /* STRUCTURE CONTAINS AN ENTRY FOR EACH DRC IN A PHYSICAL */ 15500000 /* LIBRARY. FOR EACH ENTRY THE PHYSICAL SA(FOR DRC) AND ITS */ 16000000 /* LOGICAL CONNECTION IS GIVEN. @Y30LB52*/ 16500000 /* @Y30LB52*/ 17000000 /* */ 17500000 /***************************************************************/ 18000000 18500000 LTPDRDP PTR(31), /* LOGICAL TO PHYSICAL TABLE BASE 19000000 @Y30LB52*/ 19500000 1 LTPDRDTB CHAR(8) BDY(HWORD) BASED(LTPDRDP),/* LOGICAL TO 20000000 PHYSICAL SA-CONTROLLER 20500000 CONNECTION TABLE @Y30LB52*/ 21000000 2 LTPDRC(4) CHAR(2), /* FOUR CONTROLLERS MAXIMUM PER 21500000 CARTRIDGE STORE @Y30LB52*/ 22000000 3 DRCL0 CHAR(1), /* SA AND LOGICAL CONNECTION FOR 22500000 FIRST INTERFACE @Y30LB52*/ 23000000 3 DRCL1 CHAR(1), /* SA CNTN AND LOGICALNO. 23500000 @Y30LB52 24000000 */ 24500000 @EJECT; 25000000 25500000 /***************************************************************/ 26000000 /* */ 26500000 /* @Y30LB52*/ 27000000 /* FOR EACH MSC, THERE IS A SA ARRAY @Y30LB52*/ 27500000 /* @Y30LB52*/ 28000000 /* */ 28500000 /***************************************************************/ 29000000 29500000 1 SADRDDSD(16) CHAR(8) BDY(WORD) BASED,/* TWO LOWER LEVEL 30000000 POINTERS FOR EACH SA @Y30LB52*/ 30500000 2 SADRDACC PTR(31), /* PTR TO DRD ACCUMULATORS */ 31000000 2 SADASDAC PTR(31), /* PTR TO DASD ACCUMULATORS */ 31500000 CSADRDDS CHAR(128) DEF(SADRDDSD),/* CHARACTER MAP OF THE ABOVE 32000000 ARRAY @Y30LB52*/ 32500000 33000000 /***************************************************************/ 33500000 /* */ 34000000 /* @Y30LB52*/ 34500000 /* FOR EACH SA, THERE IS A SEPARATE SET OF ACCUMULATORS@Y30LB52*/ 35000000 /* @Y30LB52*/ 35500000 /* */ 36000000 /***************************************************************/ 36500000 37000000 DRDACCTB(4,4) CHAR(6) BDY(HWORD) BASED,/* ARRAY OF ERROR 37500000 ACCUMULATORS FOR AN ENTIRE 38000000 LIBRARY @Y30LB52*/ 38500000 CDRDACCT CHAR(96) DEF(DRDACCTB),/* CHARACTER MASK FOR THE 39000000 ACCUMULATOR ARRAY @Y30LB52*/ 39500000 1 DRDACCS BASED, /* THREE ERROR TYPES @Y30LB52*/ 40000000 2 DRDERRS FIXED(15), /* DRD ERRORS @Y30LB52*/ 40500000 2 CTLIERRS FIXED(15), /* CTL-I INTERFACE ERRORS@Y30LB52*/ 41000000 2 DRCERRS FIXED(15), /* DRD CONTROLLER ERRORS @Y30LB52 41500000 */ 42000000 @ EJECT; 42500000 43000000 /***************************************************************/ 43500000 /* */ 44000000 /* @Y30LB52*/ 44500000 /* THIS IS THE TOP LEVEL OF AN ALTERNATE MEANS OF ACCESSING THE*/ 45000000 /* STRUCTURE OF HOST/SA DASD ERROR ACCUMULATORS. THIS IS AN */ 45500000 /* ARRAY OF POINTERS TO THE 'CHCUTAB' ENTRIES BASED ON 'SA' */ 46000000 /* NUMBER AND INTERFACE. @Y30LB52*/ 46500000 /* @Y30LB52*/ 47000000 /* */ 47500000 /***************************************************************/ 48000000 48500000 SAINTF(3) PTR(31) BASED, /* ONE POINTER FOR EACH UPPER 49000000 INTERFACE ATTACHED TO A HOST 49500000 CHANNEL @Y30LB52*/ 50000000 50500000 /***************************************************************/ 51000000 /* */ 51500000 /* @Y30LB52*/ 52000000 /* THIS STRUCTURE MAPS THE TABLE EQUATING CPU/CH/CU @Y30LB52*/ 52500000 /* IDENTIFICATIONS TO ABSOLUTE STORAGE ADAPTOR UPPER @Y30LB52*/ 53000000 /* INTERFACES. THIS TABLE ALSO PROVIDES A POINTER, FOR EACH */ 53500000 /* INTERFACE, TO AN ARRAY OF ACCUMULATORS FOR ERRORS IN A DASD */ 54000000 /* PATH. @Y30LB52*/ 54500000 /* @Y30LB52*/ 55000000 /* */ 55500000 /***************************************************************/ 56000000 56500000 1 CHCUTAB CHAR(12) BDY(WORD) BASED,/* CHANNEL AND CONTROL UNIT 57000000 TO SA TABLE @Y30LB52*/ 57500000 2 CPUIDSER CHAR(5), /* HOST SERIAL @Y30LB52*/ 58000000 2 CHCU CHAR(1), /* CHANNEL/CONTROL UNIT IDS */ 58500000 2 SA CHAR(1), /* SA NUMBER @Y30LB52*/ 59000000 2 INTF CHAR(1), /* WHICH INTERFACE @Y30LB52*/ 59500000 2 SPLTABP PTR(31), /* PTR TO SPINDLE ACCUMULATORS */ 60000000 60500000 /***************************************************************/ 61000000 /* */ 61500000 /* @Y30LB52*/ 62000000 /* FOR EACH SA AND UPPER INTERFACE(B, C, D), THERE IS A SET OF */ 62500000 /* ACCUMULATORS, ONE FOR EACH LOGICAL CONTROLLER AND PHYSICAL */ 63000000 /* DRIVE @Y30LB52*/ 63500000 /* @Y30LB52*/ 64000000 /* */ 64500000 /***************************************************************/ 65000000 65500000 SPNDLETB(4,8) CHAR(6) BDY(HWORD) BASED,/* SPINDLE ACCUMULATORS */ 66000000 CSPNDLET CHAR(192) DEF(SPNDLETB),/* CHARACTER MAP @Y30LB52*/ 66500000 1 SPNDLES BASED, /* THREE RECORDED ERRORS @Y30LB52*/ 67000000 2 DRVEQCHK FIXED(15), /* DRIVE CHECKS @Y30LB52*/ 67500000 2 STCTLCHK FIXED(15), /* STORAGE CONTROL CHECKS@Y30LB52*/ 68000000 2 STCTLCCK FIXED(15), /* STORAGE CONTROL CONTROL CHECKS 68500000 @Y30LB52 69000000 */ 69500000 @EJECT; 70000000 70500000 /***************************************************************/ 71000000 /* */ 71500000 /* @Y30LB52*/ 72000000 /* THIS STRUCTURE MAPS THE HEADER OF THE FIRST BLOCK OF DYNAMIC*/ 72500000 /* STORAGE OBTAINED. @Y30LB52*/ 73000000 /* @Y30LB52*/ 73500000 /* */ 74000000 /***************************************************************/ 74500000 75000000 1 P0WORK BDY(WORD) BASED(PAD00PTR), 75500000 2 PADFPTR PTR(31), /* NEXT BLOCK ADDRESS @Y30LB52*/ 76000000 2 PADLASTB PTR(31), /* LAST BLOCK ADDRESS @Y30LB52*/ 76500000 2 COREASG PTR(31), /* NEXT AVAILABLE BYTE @Y30LB52*/ 77000000 2 ENDCORE PTR(31), /* END OF BLOCK @Y30LB52*/ 77500000 78000000 /***************************************************************/ 78500000 /* */ 79000000 /* @Y30LB52*/ 79500000 /* THE HIGHEST LEVEL CONTAINS MSC UNIT ADDRESSES AND A POINTER */ 80000000 /* TO AN SA TABLE @Y30LB52*/ 80500000 /* @Y30LB52*/ 81000000 /* */ 81500000 /***************************************************************/ 82000000 82500000 2 MSCDRDAC(8) CHAR(8) BDY(WORD), 83000000 3 MSCINTF CHAR(2), /* MSC UNIT ADDRESS @Y30LB52*/ 83500000 3 * CHAR(2), 84000000 3 SATABPTR PTR(31), /* POINTER TO THE SA LEVEL */ 84500000 85000000 /***************************************************************/ 85500000 /* */ 86000000 /* TOTAL ERROR ACCUMULATOR FOR CARTRIDGE STORE'S AND MSC'S */ 86500000 /* */ 87000000 /***************************************************************/ 87500000 88000000 2 CSFTOTAL(4) FIXED(15), /* CS TOTALS @Y30LB52*/ 88500000 2 MSCTOTAL FIXED(15), /* TOTAL ERRORS FOR MSC(DASD) 89000000 @Y30LB52*/ 89500000 2 HTOTAL FIXED(15), /* TOTAL ERRORS FROM HOST(DASD) 90000000 @Y30LB52*/ 90500000 91000000 /***************************************************************/ 91500000 /* */ 92000000 /* @Y30LB52*/ 92500000 /* THIS STRUCTURE MAPS THE HEADER OF ALL BLOCKS AFTER THE */ 93000000 /* FIRST. @Y30LB52*/ 93500000 /* @Y30LB52*/ 94000000 /* */ 94500000 /***************************************************************/ 95000000 95500000 1 P0WORK1 BDY(WORD) BASED, 96000000 2 PADFPTR1 PTR(31); 96500000